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Data Sheet
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CDK3402/CDK3403
8-bit, 100/150MSPS, Triple Video DACs
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
features
n n n n n n n n n n
General Description
CDK3402/3401 products are low-cost triple D/A converters that are tailored to fit graphics and video applications where speed is critical. Two speed grades are available: CDK3402 at 100MSPS and CDK3403 at 150MSPS. TTL-level inputs are converted to analog current outputs that can drive 25-37.5 loads corresponding to doubly-terminated 50-75 loads. A sync current following SYNC input timing is added to the IOG output. BLANK will override RGB inputs, setting IOG, IOB and IOR currents to zero when BLANK = L. Although appropriate for many applications, the internal 1.235V reference voltage can be overridden by the VREF input. Few external components are required, just the current reference resistor, current output load resistors, and decoupling capacitors. Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is guaranteed from 0 to 70C.
8-bit resolution 150 megapixels per second 0.2% linearity error Sync and blank controls 1.0Vpp video into 37.5 or 75 load Internal bandgap voltage reference Double-buffered data for low distortion TTL-compatible inputs Low glitch energy Single +5V power supply
applications
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Video signal conversion - RGB - YCBCR - Composite, Y, C Multimedia systems Image processing True-color graphics systems
Block Diagram
SYNC BLANK SYNC
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G7-0
8
8-bit D/A Converter
IO G
Rev 1B
B7-0
8
8-bit D/A Converter
IO B
R7-0 CLOCK
8
8-bit D/A Converter
IO R COMP R REF V REF
+1.235V Ref
Ordering Information
Part Number CDK3402CTQ48 CDK3402CTQ48Y CDK3403CTQ48 CDK3403CTQ48Y Package TQFP-48 TQFP-48 TQFP-48 TQFP-48 Pb-Free Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Operating Temp Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C Packaging Method Package Quantity Tray Tray Tray Tray 250 1,250 250 1,250
Moisture sensitivity level for all parts is MSL-3.
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Pin Configuration TQFP-48
GND R7 R6 R5 R4 R3 R2 R1 R0 GND GND NC
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
48 47 46 45 44 43 42 41 40 39 38 37 GND G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC VDD 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25
TQFP CDK3402/3403
RREF VREF COMP IOR IOG VDD VDD IOB GND GND CLOCK NC
Pin Assignments
Pin No. 26 47-40 9-2 23-16 controls 11 10 Video outputs 33 32 29 35 36 34 12, 30, 31 1, 14, 15, 27, 28, 38, 39, 48 13, 24, 25, 37 IOR IOG IOB VREF RREF COMP VDD GND Red Current Output Green Current Output Blue Current Output Voltage Reference Output/Input Current-Setting Resistor Compensation Capacitor Power Supply Ground SYNC BLANK Sync Pulse Input Blanking Input Pin Name CLK R7-0 G7-0 B7-0 Description Clock Input Red Pixel Data Inputs Green Pixel Data Inputs Blue Pixel Data Inputs clock and pixel i/o
NC GND GND B0 B1 B2 B3 B4 B5 B6 B7 NC
13 14 15 16 17 18 19 20 21 22 23 24
Rev 1B
Voltage reference
power and Ground
NC
No Connect
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
Parameter Power Supply Voltage VDD (Measured to GND) Inputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Outputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Short Circuit Duration (single output in HIGH state to GND) Temperature Operating, Ambient Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage
Min -0.5 -0.5 -10.0 -0.5 -60.0
Max 7.0 VDD + 0.5 10.0 VDD + 0.5 60.0 unlimited 110 150 300 220 150
Unit V V mA V mA sec C C C C C
-20
-65
notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
Recommended Operating Conditions
Symbol
VDD fS tPWH tPWL tW tS th VREF CC RL VIH VIL TA
Parameter Power Supply Voltage Conversion Rate CLK Pulsewidth, HIGH CLK Pulsewidth, LOW CLK Pulsewidth Input Data Setup Time Input Date Hold Time Reference Voltage, External Compensation Capacitor Output Load Input Voltage, Logic HIGH Input Voltage, Logic LOW Ambient Temperature, Still Air CDK3402 CDK3403 CDK3402 CDK3403 CDK3402 CDK3403 CDK3402 CDK3403
Min 4.75
Typ 5.0
Max 5.25 100 150
Unit V MSPS MSPS ns ns ns ns ns ns ns ns V F V V C
Rev 1B
3.1 2.5 3.1 2.5 10 6.6 1.7 0 1.0
1.235 0.1 37.5
1.5
2.0 GND 0
VDD 0.8 70
(c)2008 CADEKA Microcircuits LLC
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3
Data Sheet
Electrical Characteristics
(TA = 25C, VDD = +5V, VREF = 1.235V, RL = 37.5, RREF = 540; unless otherwise noted)
symbol
IDD PD RO CO IIH IIL IREF VREF VOC CDI
parameter
Power Supply Current Output Resistance Output Capacitance Input Current, HIGH Input Current, LOW VREF Input Bias Current Reference Voltage Output Output Compliance Digital Input Capacitance
(1)
conditions
VDD = 5.25V, TA = 0C VDD = 5.25V, TA = 0C
Min
typ
Max
125 655
units
mA mW
Total Power Dissipation(1)
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
100 IOUT = 0mA VDD = 5.25V, VIN = 2.4V VDD = 5.25V, VIN = 0.4V 0 1.235 Referred to VDD -0.4 0 4 +1.5 10 30 -5 5 100
k pF A A A V V pF
notes: 1. 100% tested at 25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
Switching Characteristics
(TA = 25C, VDD = +5V, VREF = 1.235V, RL = 37.5, RREF = 590; unless otherwise noted)
symbol
tD tSKEW tR tF
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
parameter
Clock to Output Delay Output Skew Output Risetime Output Falltime
conditions
VDD = 4.75V, TA = 0C 10% to 90% of Full Scale 90% to 10% of Full Scale
Min
typ
10 1
Max
15 2 3 3
units
ns ns ns ns
System Performance Characteristics
(TA = 25C, VDD = +5V, VREF = 1.235V, RL = 37.5, RREF = 590; unless otherwise noted)
symbol
INL DNL EDM PSRR
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
parameter
Integral Linearity Error Differential Linearity Error DAC to DAC Matching Power Supply Rejection Ratio
conditions
Min
typ
0.2 0.2 5
Max
0.3 0.3 10 0.05
units
%/FS %/FS % %/%
Rev 1B
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Table 1. Output Voltage vs. Input Code, SYNC and BLANK, VREF = 1.235V, RREF = 590, RL = 37.5
rGB7-0 (MsB...lsB) Blue anD reD sYnc BlanK Vout sYnc Green BlanK Vout
1111 1111 1111 1111 1111 1110 1111 1101 * * 0000 0000 1111 1111 * * 0000 0010 0000 0001 0000 0000 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX
X X X X * * X X * * X X X X X X X
1 1 1 1 * * 1 1 * * 1 1 1 1 0 0 1
0.7140 0.7140 0.7134 0.7127 * * 0.3843 0.3837 * * 0.0553 0.0546 0.0540 0.0540 0.0000 0.0000 valid
1 0 1 1 * * 1 1 * * 1 1 1 0 1 0 0
1 1 1 1 * * 1 1 * * 1 1 1 1 0 0 1
1.0000 0.7140 0.9994 0.9987 * * 0.6703 0.6697 * * 0.3413 0.3406 0.3400 0.054 0.2860 0.0000 valid
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
tPWL
CLK
tPWH
1/fs
ts
Pixel Data and Controls Data N
tH
Data N+1 Data N+2
Rev 1B
3%/FS 90% tSET tF 10% tR
tD OUTPUT 50%
Figure 1. CDK3402/3403 Timing Diagram
(c)2008 CADEKA Microcircuits LLC
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5
Data Sheet
Functional Description
Within the CDK3402/3403 are three identical 8-bit D/A converters, each with a current source output. External loads are required to convert the current to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC = H activates, sync current from IOS for syncon-green video signals.
which offsets the current output. If BLANK = Low, data inputs and the pedestal are disabled. Sync Pulse Input - SYNC Bringing SYNC LOW, turns off a 40 IRE (7.62mA) current source which forms a sync pulse on the Green D/A converter output. SYNC is registered on the rising edge of CLK with the same pipeline latency as BLANK and pixel data. SYNC does not override any other data and should be used only during the blanking interval. Since this is a single-supply D/A and all signals are positive-going, sync is added to the bottom of the Green D/A range. So turning SYNC OFF means turning the current source ON. When a sync pulse is desired, the current source is turned OFF. If the system does not require sync pulses from the Green D/A converter, SYNC should connected to GND. Blanking Input - BLANK When BLANK is LOW, pixel inputs are ignored and the D/A converter outputs fall to the blanking level. BLANK is registered on the rising edge of CLK and has the same pipeline latency as SYNC.
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on the rising edge of the CLK signal. Following one stage of pipeline delay, the analog output changes tDO after the rising edge of CLK. Clock Input - CLK The clock input is TTL-compatible and all pixel data is registered on the rising edge of CLK. It is recommended that CLK be driven by a dedicated TTL buffer to avoid reflection induced jitter, overshoot, and undershoot. Pixel Data Inputs - R7-0, B7-0, G7-0 TTL-compatible Red, Green and Blue Data Inputs are registered on the rising edge of CLK.
D/A Outputs
Each D/A output is a current source. To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. Normally, a source termination resistor of 75 is connected between the D/A current output pin and GND near the D/A converter. A 75 line may then be connected with another 75 termination resistor at the far end of the cable. This "double termination" presents the D/A converter with a net resistive load of 37.5. The CDK3402/3403 may also be operated with a single 75 terminating resistor. To lower the output voltage swing to the desired range, the nominal value of the resistor on RREF should be doubled. R, G, and B Current Outputs - IOR, IOG, IOB The R, G, and B current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 lines. Sync pulses may be added to the Green D/A output.
6
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 2 and Table 1, on the previous page) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source that is connected to the green D/A converter. SYNC = H adds a 40 IRE sync pulse to the green output, SYNC = L sets the green output to 0.0V during the sync tip. SYNC and BLANK are registered on the rising edge of CLK.
Rev 1B
Data: 660mV max.
Pedestal: 54mV Sync: 286mV
Figure 2. Normal Output Levels BLANK gates the D/A inputs and sets the pedestal voltage. If BLANK = HIGH, the D/A inputs are added to a pedestal
(c)2008 CADEKA Microcircuits LLC
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Data Sheet
Current-Setting Resistor - RREF Full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. Nominal value of RREF is found from: RREF = 9.1 (VREF/IFS) where IFS is the full-scale (white) output current (in amps) from the D/A converter (without sync). Sync is 0.4 * IFS. D/A full-scale (white) current may also be calculated from: IFS = VFS/RL Where VFS is the white voltage level and RL is the total resistive load () on each D/A converter. VFS is the blank to full-scale voltage.
A 0.1F capacitor must be connected between the COMP pin and VDD to stabilize internal bias circuitry and ensure low-noise operation. Voltage Reference Output/Input - VREF An internal voltage source of +1.235V is output on the VREF pin. An external +1.235V reference may be applied here which overrides the internal reference. Decoupling VREF to GND with a 0.1F ceramic capacitor is required.
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
Power and Ground
Required power is a single +5.0V supply. To minimize power supply induced noise, analog +5V should be connected to VDD pins with 0.1F and 0.01F decoupling capacitors placed adjacent to each VDD pin or pin pair. The high slew-rate of digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance.
Voltage Reference
All three D/A converters are supplied with a common voltage reference. Internal bandgap voltage reference voltage is +1.235V with a 3k source resistance. An external voltage reference may be connected to the VREF pin, overriding the internal voltage reference.
Rev 1B
(c)2008 CADEKA Microcircuits LLC
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7
Data Sheet
Equivalent Circuits
V DD V DD
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
p n Digital Input n OUT GND GND V DD p
Figure 3. Equivalent Digital Input Circuit
Figure 4. Equivalent Analog Output Circuit
V DD
p R REF V REF
p
GND
Rev 1B
Figure 5. Equivalent Analog Input Circuit
(c)2008 CADEKA Microcircuits LLC
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8
Data Sheet
Typical Application Diagrams
75 Video Cables 75
2 IN2 OUT2 7
IOR
1
IN1
OUT1
8
75
220F
R
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
CDK3402/ CDK3403
IOG
75 75 220F
G
75
75
IOB 3 IN3
CLC3800
OUT3 6
75
220F 75
B
75
+3V or +5V
4 +Vs GND 5
1.0F
0.1F
DVD Player or STB
AC-Coupling Caps are Optional
Figure 6. Standard Definition Video Output Circuit Diagram
+Vs
IOR
+
75
CDK3402/ CDK3403
IOG
-
1/3 CLC3605
75 330
75 Video Cables
75
330
IOB
-Vs
Figure 7. Graphics Output Driver Circuit Diagram
Rev 1B
+Vs
IOR
+
75
CDK3402/ CDK3403
IOG
-
1/3 CLC3605
75 330 75
75 Video Cables
75 Video Cables
75
330
IOB
-Vs
75
75 Video Cables
75
75
Figure 8. Standard Definition Video Distribution Circuit Diagram
(c)2008 CADEKA Microcircuits LLC
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9
Data Sheet
Applications Dicussion
Figure 9 below illustrates a typical CDK3402/3403 interface circuit. In this example, an optional 1.2V bandgap reference is connected to the VREF output, overriding the internal voltage reference source.
Grounding
It is important that the CDK3402/3403 power supply is well+5V 10F 0.1F VDD RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT CLOCK SYNC BLANK R7-0 GND
regulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The CDK3402/3403 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages (VDD) come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin.
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
IOR IOG 75 75 75 COMP 0.1F V REF R REF +5V
Red
Zo = 75
75 75 75
Green w/Sync
Zo = 75
G7-0 B7-0 CLK SYNC BLANK
Blue
Zo = 75
CDK3402/3403
Triple 8-bit D/A Converter
IOB
(not required without external reference)
3.3k
LM185-1.2 590
(Optional)
0.1F
Figure 9. Typical Interface Circuit Diagram
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The CDK3402/3403 should be located near the board edge, close to the analog out-put connectors. 2. Power plane for the CDK3402/3403 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the CDK3402/3403 is the same as that of the system's digital circuitry, power to the CDK3402/3403 should be decoupled with 0.1F and 0.01F capacitors and iso-lated with a ferrite bead.
3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. 4. If the digital power supply has a dedicated power plane layer, it should not be placed under the CDK3402/3403, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the CDK3402/3403 and its related analog circuitry can have an adverse effect on performance. 5. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Evaluation boards are available (CEB3402 and CEB3403), contact CADEKA for more information.
Rev 1B
Related Products
n n
CDK3400/3401 Triple 10-bit 100/150MSPS DACs CDK3404 Triple 8-bit 180MSPS DAC
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Mechanical Dimensions
TQFP-48 Package
CDK3402/CDK3403 8-bit, 100/150MSPS, Triple Video DACs
Rev 1B
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved.
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